1. Field of the Invention
The present invention relates generally to a system that uses an anticipatory signal to regulate the output of a power supply in the system, and more particularly to a memory test system that utilizes a signal which anticipates a load change to regulate the power supply output to compensate for the load changes before they occur, thereby minimizing voltage deviation at the load.
2. Description of the Related Art
Memory tests on random access memory (RAM) integrated circuits, such as DRAMs and RAMs and the like are typically performed by the manufacturer during production and fabrication and also by a downstream manufacturer of a computer or processor controlled system at the fabrication manufacturer level to determine if the circuits are operating as intended. The testing is typically performed by a memory controller or processor (or a designated processor in a multi processor machine) which runs a testing program.
Random access memories include an array of memory cells arranged in rows and columns. After packaging, a plurality of tests are typically performed on the device in order to determine whether there is an actual or latent defect in one or more of the memory cells which would render a memory unreliable. For example, to determine if a hidden defect exists, random access memories are typically subjected to data retention tests and/or data march tests. In data retention tests, every cell of the memory is written and checked after a pre-specified interval to determine if leakage current has occurred that has affected the stored logic state. In a march test, a sequence of read and/or write operations is applied to each cell, either in increasing or decreasing address order. To determine if there is a defect in the array of bits that may fail over time, burn-in testing is typically performed to accelerate failure using voltage and temperature stress. When a failed memory cell is detected through testing, the column or row in which the failed memory cell is located is typically substituted by a redundant column or row of memory cells.
In order to reduce the time required to perform the testing of memory chips, the testing process is performed on a plurality of memory devices simultaneously. In addition, automated testing systems have been developed to further reduce the time required and simplify the testing process of memory devices.
FIG. 1 illustrates in block diagram form a conventional testing system used to perform tests on integrated circuits such as memory devices. Test system 20 generally comprises a processor 22, which controls a test device 24. Test device 24 is connected to a device under test (DUT) 26. DUT 26 contains the memory devices being tested. DUT 26 is connected to test device 24 by a communication path 28, and can be placed separate from test device 24 in order to perform environmental testing. For example, burn-in testing is typically performed at an elevated ambient temperature in a thermal chamber. Power supply 28 supplies power (Vload) to DUT 26 for operation via conductor 30.
The typical operation of test system 20 is as follows. The memory devices desired to be tested are placed onto DUT 26. Typically, a plurality of memory devices, such as for example, a group of 256 memory devices, will be tested together at the same time. Processor 22 executes a program to control test device 24 to run through a test sequence. Test device 24, in response to the signals from processor 22, performs various tests on each memory device on DUT 26, such as data retention, data march, and burn-in tests previously discussed. Typically, each test is performed on every memory device on DUT 26 simultaneously. Based on the results of the tests performed, test device 24 determines if a memory device on DUT 26 is faulty. Power is supplied to DUT 26 by power supply 28, since it is necessary to have the memory devices powered in order to properly test them.
There are some problems, however, with the conventional test system 20 as illustrated in FIG. 1. Each memory device on DUT 20 has a required power supply rating, i.e. operating voltage, with a certain tolerance. To prevent malfunctioning of the memory device, or in some cases even damage to the memory device, it is important to maintain the supply voltage within the tolerance of the rated supply voltage. Power supply 28 is typically designed to provide the proper voltage to the memory devices on DUT 26. Additionally, power supply 28 typically includes some type of feedback circuit or circuits, as are known in the art, to compensate for changes in the load current which may cause deviations in the supply voltage. There are several dynamic variables that may influence the load current required by DUT 26 during a test sequence, such as the number of devices under test and the specific test being performed. In addition, static variables such as the impedance of the conductor 30 between power supply 28 and DUT 26 can also contribute to a deviation, such as a voltage drop, in the supply voltage. Although the impedance of conductor 30 is typically very small, for example less than 0.01 ohms, when large currents are passed through conductor 30, there will be an associated voltage drop across conductor 30. While the voltage drop across conductor 30 may only be in the range of tenths or hundredths of a volt, this may be significant enough to adversely impact upon the supplied operating voltage to the memory devices.
Sudden changes in the load current cause the output voltage of power supply 28 to deviate for a short period of time until a negative feedback circuit of power supply 28 can adjust the output voltage. The greater the increase or decrease in the load current, the greater the deviation in the output voltage of power supply 28. Thus, the feed back circuit provided in power supply 28 monitors the output voltage and adjusts it accordingly should an increase or decrease in the output voltage, caused by a change in the load current, be detected. Such a feedback system, however, may not be suitable to adequately adjust the output voltage when a relatively large change in the load current is experienced over a short period of time. In test system 20, up to several hundred memory devices may be under test simultaneously. During the performance of the tests, since each memory device performs the same test operation simultaneously and each memory device requires power to operate, the load current required by DUT 26 can increase from 0 to 20 Amperes in as little as 100 .mu.s.
FIG. 2 illustrates a waveform for the output voltage Vload of power supply 28 that is applied to DUT 26. Vload represents the operating voltage rating of each memory device on DUT 26, and may be for example 3 V .+-.0.2 V. Thus, the minimum input voltage, represented by Vmin, would be 2.8 V in this example and the maximum input voltage, represented by Vmax, would be 3.2 V in this example. At time t.sub.1, a test is initiated by test device 24 that requires each memory device on DUT 26 to perform some operation that requires an increase in its drawn current. While the increase in drawn current by each memory device on DUT 26 is relatively small, the increase in the current drawn by DUT 26 is the sum of drawn currents for every memory device on DUT 26 and can be significant, such as the 20 A noted above. As the load increases, the output voltage Vload of power supply 28 will decrease. The feedback circuit of power supply 28 will sense the decrease in Vload, and at some time t.sub.2 will operate to adjust Vload in response. However, if there is a significant load change in a short period of time, the feedback system may be unable to adjust in time to prevent output voltage Vload from falling below Vmin, as illustrated. Additionally, the feedback circuit of power supply 28 may overcompensate for the load change, and at some time t.sub.3 the output voltage Vload may increase above Vmax. At time t.sub.4, the output voltage Vload levels off to the proper level.
Thus, there exists a need for a test system and power supply that are capable of compensating for large changes in the load in a short time period while maintaining the supply voltage within acceptable tolerance levels.